1. Field of the Invention
The present invention relates to burst SRAMs designed to operate at a given data rate corresponding to a first clock signal on a second, faster clock signal.
2. Description of the Related Art
The consumers constantly demand faster and more powerful computers from the computer industry. A major bottleneck in computer speed has historically been the speed with which data can be accessed from memory, where this speed is referred to as the memory access time. The microprocessor, with its relatively fast processor cycle times, has generally had to wait during memory accesses to account for the relatively slow memory devices. Therefore, improvement in memory access times has been one of the major areas of research in enhancing computer performance.
In order to bridge the gap between fast processor cycle times and slow memory access times, cache memory was developed. A cache is a small amount of very fast, expensive, preferably zero wait state memory that is used to store a copy of frequently accessed code and data from system memory. The microprocessor can operate out of this very fast memory and thereby reduce the number of wait states that must be interposed during memory accesses.
The i486 microprocessor by the Intel Corporation (Intel) uses a 32-bit data path and includes a version which operates with 33 or 50 MHz clocks. The C5 or cache controller and compatible C8 or 82490 cache static random access memories (SRAMs) are designed for use with the i486 microprocessor to provide a relatively high performance microprocessor/cache system operating at 33 or 50 MHz. Another memory chip compatible with the i486 microprocessor is the MCM62486A 32k.times.9 BurstRAM synchronous SRAM from Motorola, Inc., which is designed for use in a burstable, high performance, secondary level cache for the i486 microprocessor. This particular burst SRAM was designed to operate with a 33 MHz clock.
The P5 or Pentium microprocessor from Intel is a next generation microprocessor offering very high performance features, including superscaler architecture and integrated and separate code and data caches. One version of the P5 operates at a clock speed of 66 MHz and uses a full 64-bit data path, thereby providing significant performance improvements over the 32-bit, 33 MHz i486 microprocessor. Intel provides a C5C cache controller with corresponding C8C SRAMs, which provides an optimal second level cache system for use with the P5 microprocessor. The C5C cache controller and C8C SRAMs, however, are very costly. Furthermore, other design considerations and limitations involved in the use of the C5C and C8C cache combination make other alternatives more attractive, especially from the standpoint of simplicity, convenience and cost.
Standard SRAMs typically operate at 60 to 80 nanoseconds (ns), and thus are not capable of keeping up with the desired transfer rate of cache memory subsystems associated with the P5 microprocessor. Burst SRAMs capable of operating at less than 30 ns corresponding to a 33 MHz clock are desirable for use with the P5 microprocessor to prevent excessive wait states.
It is desirable to use a 66 MHz version of the P5 microprocessor in conjunction with faster burst SRAMs designed for use with 33 MHz clock speeds, primarily for cost and simplicity reasons. For proper operation in systems using a microprocessor operating at a faster speed than memory devices, however, it is typical to provide extra clock and synchronization circuitry for receiving the faster clock and dividing it down to a slower clock for use by slower memory devices. The synchronization circuitry must insert delays so that the memory devices are synchronized to the slower clock. For example, it is desirable that every rising edge of the slower clock correspond with every other rising edge of the faster clock in a two clock system. The faster logic, such as the CPU, may initiate operations on any rising edge of the fast clock. However, logic operating off the slower clock speed must initiate operations upon the rising edge of its slower clock. This results in substantial additional delays in a synchronized system, since the microprocessor may initiate a cycle on an "odd" clock cycle, where the slower devices must wait for the rising edge of the slower clock.
It is desirable, therefore, to avoid the expense and delays of additional clock and synchronization circuitry associated with generating and synchronizing a slower clock signal from the system clock for use by slower memories.